1. Technical Field
The invention relates to the use of voltage-controlled oscillators and more particularly to systems that may employ multiple voltage-controlled oscillators.
2. Background of the Invention
Generally, a voltage-controlled oscillator (VCO) is an essential circuit, such as in phase-locked loop (PLL) systems, and is typically used to provide an output signal whose frequency is tunable with a control voltage (tuning voltage) typically referred to as Vtune. The tuning voltage typically varies from a minimum of about a fixed voltage V1 (e.g., 0.3 V) to a maximum voltage, typically referred to as VCC, minus a fixed voltage V2 (e.g. 2.7 V-0.5 V=2.2 V). Fixed voltages V1 and V2 are dependent on the type of charge pump that the PLL uses.
A VCO has a limited amount of tuning range. The tuning range depends, e.g., on the amount of tuning voltage Vtune that is available, and on a varactor used by the VCO. The ratio of the frequency range and the tuning voltage is referred to as VCO sensitivity (Kxcexd). Low-sensitivity VCOs are often desirable to provide good circuit characteristics to reduce or minimize noise.
A number of technical advances are achieved in the art to provide a PLL capable of synthesizing frequencies over a wide frequency range. This is achieved by employing multiple VCOs, with overlapping frequency ranges, in conjunction with a tuning circuit. The tuning circuit may be broadly conceptualized as a system that may determine, and/or select, which of multiple VCOs of the PLL to use for a desired output oscillation frequency. Using such a system, a PLL can seamlessly lock to a wide range of frequencies using the multiple VCOs. The tuning circuit may determine and select which VCO to use, and tune the PLL, without using any devices located, or signals from, off chip relative to the PLL. The tuning circuit may also help reduce, and even minimize, the number of VCOs used to cover a particular frequency range.
For example, a tuning circuit in the PLL may receive signals indicative of various frequencies and may determine which VCO to use for each signal according to the indicated frequency. An implementation of the system architecture may include a comparator, a loop filter, a binary search algorithm circuit (BSAC), a PLL mapping encoder, and a VCO selector. In a calibration mode, a VCO is selected and the comparator compares an output voltage of the loop filter with an on-chip reference voltage. The BSAC uses an output of the comparator to determine the range of the selected VCO. In particular, the BSAC iteratively produces indications of test words to apply to the selected VCO. The PLL mapping encoder scales the BSAC indications and provides N-bit multipliers to the PLL containing multiple VCOs. The PLL attempts to lock to the desired test frequencies using the VCO selected by the VCO selector. The BSAC responds to whether the PLL locks to the test frequencies by adjusting, as appropriate, the indication from the BSAC, and thus the frequency to which the PLL attempts to lock. A record indicative of the VCO to select depending upon an indicated frequency is stored in the VCO selector. In a normal operation mode, in response to an incoming signal being received, the VCO selector uses an indication of a frequency from the incoming signal and the stored record to select an appropriate VCO to use to lock to the frequency indicated by the incoming signal.